1. Field of the Invention
The present invention relates to a signal output circuit formed in a semiconductor integrated circuit and, more particularly, to a signal output circuit capable of suppressing power supply noise generated when an output signal is changed and suppressing leakage of the power supply noise to an output node.
2. Description of the Related Art
In a semiconductor integrated circuit, when the output from an output buffer circuit is to be changed, an increase or decrease in power supply potential or ground potential is caused by an induced electromotive voltage determined by a product "L.times.di/dt" where L is an inductance of a power supply line or a ground line and di/dt is a rate of change in output current. These potential variations become power noise to be transmitted to an output node through a transistor constituting part of the output buffer circuit to cause output noise. Especially, when a plurality of output buffers perform switching operations simultaneously, the output noise is increased to cause problems. Such noise is called simultaneous switching noise (SSN).
Recently, as the micropatterning size of a semiconductor element is decreased to increase the operation speed, the potential variations are increased. Then, the SSN causes an erroneous operation of a circuit in the same integrated circuit or of an input circuit of other integrated circuit to which the output from the output buffer circuit is input. Especially, when outputs from a plurality of output buffer circuits of the same integrated circuit vary simultaneously, the potential variations become very large, posing a very serious problem.
Conventionally, in order to minimize the potential variation in the power supply or the output as described above, efforts have been made to decrease the inductance L of the power supply line or the ground line, or to decrease the rate of change di/dt in output current. The inductance L, however, is determined by the length of the lead frame of the package of the integrated circuit or the bonding wire, and it is not easy to shorten the lead frame or the bonding wire. Also, the speed of an output signal (a rise time tr or a fall time tv) and a propagation delay time tpd of a signal propagation line are normally defined as the design specifications. When di/dt is decreased, tr and tv, and thus tpd are increased, and the specified values cannot be satisfied. In other words, in order to increase the speed of the output signal, the output current of the output buffer circuit must be increased. When the speed of the output signal is determined, the lower limit of the di/dt is determined. Hence, the di/dt cannot be simply decreased, and it is difficult to minimize the potential variation.
Generally, the specifications of the output current of a signal output circuit include AC specifications (determined in accordance with the speed of the output signal) and DC specifications (a source current I.sub.OH and a sink current I.sub.OL when the output is stationary). In an integrated circuit having high-speed specifications, when the output current is determined in accordance with the AC specifications, the DC specifications are often automatically satisfied. When the output currents (I.sub.OH, I.sub.OL) of the DC specifications of the output buffer circuit are automatically determined from the AC specifications, the output resistance (an ON resistance R.sub.ON) when the output is stationary is also automatically determined. Assume that the output buffer circuit is a CMOS inverter comprising a p-channel MOS transistor and an n-channel MOS transistor. When the input signal is at Vcc level (potential of the high potential-side power supply), the p-channel MOS transistor is turned off, and the n-channel MS transistor is turned on. The ON resistance R.sub.ON (=V.sub.OL /I.sub.OL) of the n-channel MOS transistor is determined by an output potential V.sub.OL at "L" level and the sink current I.sub.OL at this time. When the input signal is at Vss level (potential of the low potential-side power supply; ground potential), the n-channel MOS transistor is turned off, and the p-channel MOS transistor is turned on. The ON resistance R.sub.ON (={(Vcc-V.sub.OH }/I.sub.OH) of the p-channel MOS transistor is determined by an output potential V.sub.OH at "H" level and the source current I.sub.OH at this time.
When the output from the signal output circuit is changed, the level of the output noise appears as a bounce quantity .DELTA.E.sub.B of the power supply potential or the ground potential divided by a rate of the ON resistance R.sub.ON of the signal output circuit to a load impedance Z of the output node. When the load impedance Z is a capacitive load (i.e., a capacitance C.sub.L), output noise V.sub.OLP when the output is at "L" level becomes substantially .DELTA.E.sub.B /(1+S.multidot./C.sub.L .multidot.R.sub.ON), and the higher the R.sub.ON, the lower the V.sub.OLP. The fact that the ON resistance R.sub.ON is automatically determined by the AC specifications of the output buffer circuit, as described above, means that when the speed of the output signal is determined, the lower limit of the output noise V.sub.OLP is determined. This applies to output noise V.sub.OHV when the output is at "H" level.
As described above, in the conventional output buffer circuit, since the ON resistance R.sub.ON, which is automatically determined from the AC specifications of the output buffer circuit, is low when compared to that determined only from the DC specifications, a variation in the power supply potential or the ground potential when the output is changed can easily adversely affect the output node, and the output noise V.sub.OLP or V.sub.OHV tends to be unpreferably increased.